Example embodiments of the inventive concepts relate to a semiconductor device and a method of fabricating the same.
As a feature size of a MOS transistor is scaled down, a width of a gate pattern and/or a length of a channel region are decreasing. Various studies have been conducted to overcome consequent technical difficulties and/or improve an operational property of the MOS transistor.
For example, a device of which a gate insulating layer and a gate electrode are formed of a high-k dielectric and a metal layer, respectively, is being studied. Since the metal layer has a poor heat-resistant property, a damascene process may be used to form the gate electrode of the device. Further, in order to realize devices with different performance on a semiconductor substrate, the devices may be formed to have gate insulating layers, whose thicknesses are different between device regions.